1. Field of the Invention
The present invention relates to a semiconductor integrated circuit of a gate array approach, a method of fabricating the same, and a method of arranging cells.
2. Description of the Background Art
In general, semiconductor integrated circuits of a gate array approach are subjected to common process steps until a transistor forming process step but are customized in a metal wiring process step. A common transistor region includes basic cells having a plurality of transistors as a basic unit and arranged regularly on an LSI chip.
An example of the gate array approach semiconductor integrated circuits is disclosed in, for example, "Nikkei Micro Device, June, 1989, `Prospective Winner of Stand-by Large-Scale Gate Arrays, Sea of Two Hundred Thousand Gates Type`, p. 94, FIG. 8" in which the basic cells are designed to facilitate the customization of a minimum gate unit for a logic suitable for arrangement of memory cells such as two-input NAND gates.
FIG. 21 is a plan view of a conventional basic cell. As shown in FIG. 21, a basic cell 41 comprises gate electrodes 42, P-type diffused regions 43, gate electrodes 44, N-type diffused regions 45, contact holes 46, and first layer metal lines 47. FIG. 22 is a cross-sectional view taken along the line A--A of FIG. 21. In FIG. 22, the reference numeral 21 designates a semiconductor chip, and 22 designates field oxide films 22.
Referring to FIGS. 21 and 22, the P-type diffused regions 43A, 43B, 43C are selectively formed in the surface of the semiconductor chip 21, and the two gate electrodes 42 are formed respectively on a region between the P-type diffused regions 43A and 43B and a region between the P-type diffused regions 43B and 43C. The gate electrodes 42 and the P-type diffused regions 43 (43A, 43B, 43C) form a PMOS transistor. On the other hand, the N-type diffused regions 45A, 45B, 45C are selectively formed in the surface of the semiconductor chip 21, and the two gate electrodes 44 are formed respectively on a region between the N-type diffused regions 45A and 45B and a region between the N-type diffused regions 45B and 45C. The gate electrodes 44 and the N-type diffused regions 45 (45A, 45B, 45C) form an NMOS transistor.
The first layer metal lines 47 (47A to 47F) for macro cell formation are selectively formed in the basic cell 41. The first layer metal lines 47B are formed over the P-type diffused regions 43 and are electrically connected to the P-type diffused regions 43 through contact holes 46. The first layer metal line 47A is a line for a power supply and is electrically connected to the first layer metal lines 47B through at least one of the contact holes 46. The first layer metal lines 47C are lines for connection between the diffused regions in the PMOS and NMOS transistors. The first layer metal lines 47D are lines for connection between the gates of the PMOS and NMOS transistors. The first layer metal lines 47E are formed over the N-type diffused regions 45 and are electrically connected to the N-type diffused regions 45 through contact holes 46. The first layer metal line 47F is a line for a ground and is electrically connected to the first layer metal lines 47E through contact holes 46.
In this manner, predetermined logic functions are set to the basic cell 41 which in turn serves as a macro cell by the electrical connections by the first layer metal lines 47 and through the contact holes 46.
Logic gates (macro cells) are customized mainly by contact holes (the contact holes 46 of FIG. 21) and first layer lines (the first layer metal lines 47 of FIG. 21) and, as the case may be, by using second layer lines and first via holes (holes for connection between the first and second layer lines).
However, various macro cells must be formed using one or more basic cells of predetermined construction, and the number and position of contacts with the diffused regions serving as source/drain regions of MOS transistors are different depending on basic cells. Thus a need exists to ensure a given area or more of the diffused regions to insure the number of contacts, which does not permit reduction in transistor gate width and, accordingly, reduction in capacitance.
The diffused regions have a resistance higher than the metal lines, and the operating characteristics of the transistors are deteriorated without good contacts being set between the diffused regions and the metal lines, resulting in changes in the operating characteristics of the macro cells formed by means of the basic cells depending on the number and position of contacts with the diffused regions.
Further, there is only one type of conventional gate array approach basic cells. Therefore, the formation of macro cells of different operating characteristics requires changes in layout (wiring pattern) of the macro cells themselves.